There is a plurality of true/complement generating circuits used with a diode selecting array or a similar device, for selecting the word or bit lines of a memory array. These generators appear as quite satisfactory in numerous applications.
For instance, such a circuit is described in publication No. 0024496 of the European Patent Application filed on June 24, 1980. (Publication No. 0024496 corresponds to U.S. Patent Application Ser. No. 179,210 entitled "Generator Circuit For Generating True/Complement Signals" filed Aug. 18, 1980 by M. Grandguillot et al., of common assignee and now abandoned.)
There is a sizeable number of true/complement circuits known and used in the art. A very large number of patents and publications are directed to true/complement circuits. Merely by way of example: (1) U.S. Pat. No. 3,222,547 entitled "Self-Balancing High Speed Transistorized Switch Driver and Inverter" granted Dec. 7, 1965 to B. H. Boan et al; (2) U.S. Pat. No. 3,535,644 entitled "Pulse Amplitude and Width Detector" granted Oct. 20, 1970 to M. D. Slayden et al.; (3) U.S. Pat. No. 3,654,490 entitled "Gate Circuit with TTL Input and Complementary Outputs" granted Apr. 4, 1972 to D. T. Kan; (4) U.S. Pat. No. 3,914,628 entitled "T-T-L Driver Circuitry" granted Oct. 21, 1975 to Henry C. Pao et al.; (5) U.S. Pat. No. 4,228,371 entitled "Logic Circuit" granted Oct. 14, 1980 to J. D. Mazgy; (6) Publication entitled "True-Complement Generator" by S. D. Koutos et al., IBM Technical Disclosure Bulletin, Vol. 14, No. 11, April 1972, page 3244; and (7) Publication entitled "In-Line Word Address True/Complement Generator" by B. A. Denis et al., IBM Technical Disclosure Bulletin, Vol. 24, No. 4, September 1981, page 2209.
Since the read and write cycles of the memory arrays are now shorter and shorter, said known circuits show a drawback which is due to the fact that the true and at complement outputs thereof change the same time. As a matter of fact, in order to select a word line amongst 2.sup.n lines in a memory array, one uses a diode decoder to which address signals are applied by means of n true/complement generators. In such an arrangement, undesired selections can appear each time the two outputs of one or more generators are simultaneously in a condition which does not ensure a deselection. This phenomenon will be explained in details with reference to FIGS. 1 and 2 of this application.